The present invention relates to the field of power over Ethernet, and more particularly to power sourcing equipment having an impedance populated path between an output port and a power input which is disabled in the absence of input power.
The growth of local and wide area networks based on Ethernet technology has been an important driver for cabling offices and homes with structured cabling systems having multiple twisted wire pairs. The ubiquitous local area network, and the equipment which operates thereon, has led to a situation where there is often a need to attach a network operated device for which power is to be advantageously supplied by the network over the network wiring. Supplying power over the network wiring has many advantages including, but not limited to; reduced cost of installation; centralized power and power back-up; and centralized security and management.
Several patents addressed to this issue exist including: U.S. Pat. No. 6,473,608 issued to Lehr et al., whose contents are incorporated herein by reference and U.S. Pat. No. 6,643,566 issued to Lehr et al., whose contents are incorporated herein by reference. Furthermore a standard addressed to the issue of powering remote devices over an Ethernet based network has been published as IEEE 802.3af-2003, whose contents are incorporated herein by reference.
An Ethernet switch or midspan module providing power over Ethernet (POE) functionality is typically designed to support a plurality of ports, and power is preferably to be supplied to compatible equipment after detection. Detection is accomplished by impressing two distinct known voltage levels via a known impedance on the device to be detected and measuring the resultant port voltages. A resistive signature of the device is determined as a result of the measured port voltages. A pre-determined signature resistance, preferably of between 19 Kohm and 26.5 Kohm, is indicative of a device to be powered. Unfortunately if the device meets the criteria of the resistive signature it will be powered irrespective of whether the device is designed to receive power over the Ethernet cabling. Furthermore, certain legacy devices require other signatures for detection. In particular, a pre-standard capacitor detection is known to the prior art, and in the event that the device meets the pre-standard detection power may be supplied irrespective of whether the device is designed to receive power over the Ethernet cabling.
Power is typically supplied under control of a POE controller, the POE controller energizing for each port to be powered an electronically controlled switch, which in an exemplary embodiment comprises a power MOSFET. In another embodiment the electronically controlled switch comprises a FET or bipolar transistor. In order to reduce cost and minimize the footprint, preferably the required electronically controlled switches are provided embedded within the POE controller. In another embodiment the required electronically controlled switches are provided external to the POE controller, and are responsive to an output of the POE controller.
After powering a port for which a valid attached powered device has been detected, the port is monitored for a valid maintain power signature (MPS). The above mentioned standard describes two MPS components; an AC MPS component and a DC MPS component. The POE controller may optionally monitor the AC MPS component, the DC MPS component or both the AC and the DC MPS components. Implementation of the AC MPS component requires an AC signal source to be connected to the port. The term AC signal source is meant to be a general term, indicative of a non-uniform signal, herein impressed onto a DC signal. In the event that the POE controller detects an absence of a valid monitored MPS component power to the port is to be disconnected. Preferably, disconnection is to occur within 300-400 ms of the dropout of a valid monitored MPS component.
FIG. 1A illustrates a high level schematic diagram of a first embodiment of a POE system arranged to monitor an AC MPS component for disconnection of a powered device according to the prior art. The POE system of FIG. 1A comprises a power sourcing equipment (PSE) 5; a powered device (PD) 10; a first twisted pair 30; a second twisted pair 35; and a power source PS. PD 10 presents a capacitance and a load schematically represented as Cload and Zload. PSE 5 comprises a POE controller 20; a sense resistor Rsense; a unidirectional current means D1; an output impendence Zout; an output capacitor Cout; and an input capacitor Cin. POE controller 20 exhibits an output port between terminals designated Vport—Pos and Vport—Neg and comprises a control circuit 40; an AC signal source 50; an AC signal source resistance Rac; an electronically controlled switch SW1; a detection source Idetect; a control means 60; a control means 70; a sensing input 80; and a control means 90.
Electronically controlled switch SW1 is illustrated as a power MOSFET, however this is not meant to be limiting in any way. SW1 may be implemented as a FET or bipolar transistor without exceeding the scope of the invention. Detection source Idetect is illustrated as being a variable current source, however this is not meant to be limiting in any way. Detection source Idetect may be implemented as a voltage source or as a plurality of current sources without exceeding the scope of the invention. Twisted pairs 30 and 35 form part of a single structured communication cabling. Cload and Zload schematically represent the input capacitance and load, respectively, of PD 10 which is to be detected and powered by PSE 5. In an exemplary embodiment Zout comprises a 45.3 K resistor, Cout comprises a 0.2 μf capacitor and Cin is typically on the order of 22-47 μf. AC signal source 50 is illustrated herein as a current source, and is a particular example of a general non-uniform signal source. Unidirectional current means D1 typically comprises a Zener diode with a breakdown voltage of approximately 10 volts.
Switch SW1 is illustrated as being internal to POE controller 20, typically as part of a single integrated circuit, however this is not meant to be limiting in any way. Switch SW1 may be implemented externally to POE controller 20 without exceeding the scope of the invention. Control means 60 may be a direct output of control circuit 40 or a circuit responsive thereto without exceeding the scope of the invention.
The positive output of power source PS is connected to the anode of unidirectional current means D1, a first end of Zout, a first end of Cin, and via a terminal designated VMain to the input of AC signal source 50, a first end of Rac and control circuit 40. The cathode of unidirectional current means D1 is connected to a first end of Cout, control circuit 40 via sensing input 80 connected to terminal Vport—Pos, a second end of Rac, the output of AC signal source 50 and a first end of first twisted pair 30. The control input of AC signal source 50 is connected to control circuit 40 via control means 90. The control input of detection source Idetect is connected to an output of control circuit 40 via control means 70. The gate of electronically controlled switch SW1 is connected to an output of control circuit 40 via control means 60. The negative output of power source PS is connected to ground, a second end of Cin and a first end of Rsense. A second end of Rsense is connected to an input of control circuit 40 and to the drain of SW1. The source of SW1 is connected to one end of detection source Idetect, to a second end of Zout via terminal Vport—Neg, a second end of Cout and a first end of second twisted pair 35. The return of detection source Idetect is connected to ground. A second end of first twisted pair 30 is connected to a first end of Zload and a first end of Cload. A second end of Zload and a second end of Cload are connected to a second end of second twisted pair 35.
In operation control circuit 40 operates detection source Idetect through control means 70 to generate a plurality of current levels. The plurality of current levels flow through Zload, if connected, thereby presenting a plurality of voltages sensed at sensing input 80. After detection and classification of a valid PD 10, control circuit 40 connects power from power source PS over first and second twisted pairs 30,35 by the operation of electronically controlled switch SW1 via control means 60. AC signal source 50, operated via control means 90, supplies an AC MPS which is sensed at sensing input 80. Among other functions, unidirectional current means D1 prevents the attenuation of the output of AC signal source 50 by blocking a connection to power source PS. Upon detection of the absence of a valid MPS, control circuit 40 operates control means 60 to open electronically controlled switch SW1 thereby disabling power to PD 10.
FIG. 1B illustrates a high level schematic diagram of a second embodiment of a POE system arranged to monitor an AC MPS component for disconnection of a PD according to the prior art. The POE system of FIG. 1B comprises a PSE 5; a PD 10; a first twisted pair 30; a second twisted pair 35; and a power source PS. PD 10 presents a capacitance and a load schematically represented as Cload and Zload. PSE 5 comprises a POE controller 20; a sense resistor Rsense; a unidirectional current means D1; an output impendence Zout; an output capacitor Cout; and an input capacitor Cin. POE controller 20 exhibits an output port between terminals designated Vport—Pos and Vport—Neg and comprises a control circuit 40; an AC signal source 55; an AC signal source resistance Rac; an electronically controlled switch SW1; a detection source Idetect; a control means 60; a control means 70; a sensing input 80; and a control means 90.
Electronically controlled switch SW1 is illustrated as a power MOSFET, however this is not meant to be limiting in any way. SW1 may be implemented as a FET or bipolar transistor without exceeding the scope of the invention. Detection source Idetect is illustrated as being a variable current source, however this is not meant to be limiting in any way. Detection source Idetect may be implemented as a voltage source or as a plurality of current sources without exceeding the scope of the invention. Twisted pairs 30 and 35 form part of a single structured communication cabling. Cload and Zload schematically represent the input capacitance and load, respectively, of PD 10 which is to be detected and powered by PSE 5. In an exemplary embodiment Zout comprises a 45.3 K resistor, Cout comprises a 0.2 μf capacitor and Cin is typically on the order of 22-47 μf. AC signal source 55 is illustrated herein as a voltage source, and is a particular example of a general non-uniform signal source.
Switch SW1 is illustrated as being internal to POE controller 20, typically as part of a single integrated circuit, however this is not meant to be limiting in any way. Switch SW1 may be implemented externally to POE controller 20 without exceeding the scope of the invention. Control means 60 may be a direct output of control circuit 40 or a circuit responsive thereto without exceeding the scope of the invention.
The positive output of power source PS is connected to the anode of unidirectional current means D1, a first end of Cin, a first end of Zout, and via a terminal designated VMain to a first end of AC signal source 55 and control circuit 40. The cathode of unidirectional current means D1 is connected to a first end of Cout, control circuit 40 via sensing input 80 connected to terminal Vport—Pos, a first end of Rac and a first end of first twisted pair 30. A second end of Rac is connected to a second end of AC signal source 55. The control input of AC signal source 55 is connected to control circuit 40 via control means 90. The control input of detection source Idetect is connected to an output of control circuit 40 via control means 70. The gate of electronically controlled switch SW1 is connected to an output of control circuit 40 via control means 60. The negative output of power source PS is connected to ground, a second end of Cin and a first end of Rsense. A second end of Rsense is connected to an input of control circuit 40 and to the drain of SW1. The source of SW1 is connected to a first end of detection source Idetect, to the second end of Zout via terminal Vport—Neg, a second end of Cout and a first end of second twisted pair 35. The return of detection source Idetect is connected to ground. A second end of first twisted pair 30 is connected to a first end of Zload and a first end of Cload. A second end of Zload and a second end of Cload are connected to a second end of second twisted pair 35.
In operation control circuit 40 operates detection source Idetect through control means 70 to generate a plurality of current levels. The plurality of current levels flow through Zload, if connected, thereby presenting a plurality of voltages sensed at sensing input 80. After detection and classification of a valid PD 10, control circuit 40 connects power from power source PS over first and second twisted pairs 30,35 by the operation of electronically controlled switch SW1 via control means 60. AC signal source 55, operated via control means 90, supplies an AC MPS which is sensed at sensing input 80. Among other functions, unidirectional current means D1 prevents the attenuation of the output of AC signal source 55 by blocking a connection to power source PS. Upon detection of the absence of a valid MPS, control circuit 40 operates control means 60 to open electronically controlled switch SW1 thereby disabling power to the port.
FIG. 1C illustrates an embodiment of a complete POE system comprising a plurality of PSEs and PDs, in which one PSE unit is inadvertently connected in error to a second PSE unit. The system of FIG. 1C comprises a first ganged power insertion equipment 95 comprising a first plurality of PSE 5, and a second ganged power insertion equipment 95 comprising a second plurality of PSE 5. First ganged power insertion equipment 95 is connected to a power source PS. A first PSE 5 of first ganged power insertion equipment 95 is connected over twisted pair cabling 30, 35 to a first PSE 5 of second ganged power insertion equipment 95. Such a connection is improper, however in the realities of crowded wiring closets such a connection does sometimes occur. Each of the remaining PSEs 5 of both first and second ganged power insertion equipment 95 are connected to a respective PD 10. It is to be noted that second ganged power insertion equipment 95 is not connected to a power source, and thus each PSE 5 of second ganged power insertion equipment 95 should not be operative to supply power to an associated PD 10.
In operation, first PSE 5 of first ganged power insertion equipment 95 operates to attempt to detect a valid PD signature resistance. Referring to FIG. 1A, it will be noted that a momentary DC path is presented across the output port of first PSE 5 of second ganged power insertion equipment 95 comprising Rac, Cin, Rsense and the parasitic diode of SW1. Referring to FIG. 1B, it will be noted that a momentary DC path is presented by first PSE 5 of second ganged power insertion equipment 95 comprising Rac, AC signal source 55, Rsense and the inherent diode of SW1. It is to be understood that once Cin charges up this path is no longer seen, however detection may be accomplished prior to the completion of the charging of Cin. Furthermore, a legacy detection as described above may detect Cin as a valid signature through the above mentioned paths.
In the event that first PSE 5 of first ganged power insertion equipment 95 detects first PSE 5 of second ganged power insertion equipment 95 as a valid device to be powered, first PSE 5 of first ganged power insertion equipment 95 will apply power, typically of a nominal 48 volts, via first and second twisted pairs 30,35. The supplied power will exceed the breakdown voltage of unidirectional current means D1, with a return path being provided by the inherent diode of SW1. A voltage will thus be applied across Cin of first PSE 5 of second ganged power insertion equipment 95 and will be detected by all other PSEs 5 in second ganged power insertion equipment 95. Control circuit 40 (not shown) of all other PSEs 5 in second ganged power insertion equipment 95 will then begin to function to detect and power their associated PD 10. Such an operation will result in the possible burnout of D1 of first PSE 5 of second ganged power insertion equipment 95, and may further lead to a burnout of switch SW1 of first PSE 5 of second ganged power insertion equipment 95.
What is needed, and not supplied by the prior art, is a means from preventing detection of a POE controller by another POE controller improperly connected thereto.